dynasmrt/
x64.rs

1//! Runtime support for the x64 architecture assembling target.
2//!
3//! The x64 instruction set features variable-length instructions and
4//! relative relocations up to 32 bits in size.
5//!
6//! The core relocation behaviour for this architecture is provided by the [`X64Relocation`] type.
7//!
8//! Next to that, this module contains the following:
9//!
10//! ## Type aliases
11//!
12//! Several specialized type aliases of the generic [`Assembler`] are provided as these are by far the most common usecase.
13//!
14//! ## Enums
15//!
16//! There are enumerator of every logically distinct register family usable in x64. 
17//! These enums implement the [`Register`] trait and their discriminant values match their numeric encoding in dynamic register literals.
18//! Some of these are re-exported from the x86 architecture.
19//!
20//! *Note: The presence of some registers listed here is purely what is encodable. Check the relevant architecture documentation to find what is architecturally valid.*
21
22use crate::Register;
23use crate::relocations::SimpleRelocation;
24
25/// The x64 architecure doesn't have special relocation encodings.
26pub type X64Relocation = SimpleRelocation;
27
28/// An x64 Assembler. This is aliased here for backwards compatability.
29pub type Assembler = crate::Assembler<X64Relocation>;
30/// An x64 AssemblyModifier. This is aliased here for backwards compatability.
31pub type AssemblyModifier<'a> = crate::Modifier<'a, X64Relocation>;
32/// An x64 UncommittedModifier. This is aliased here for backwards compatability.
33pub type UncommittedModifier<'a> = crate::UncommittedModifier<'a>;
34
35
36/// 1, 2, 4 or 8-byte general purpose "quad-word" registers.
37///
38/// RIP does not appear here as it cannot be addressed dynamically.
39#[allow(missing_docs)]
40#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
41pub enum Rq {
42    RAX = 0x0, RCX = 0x1, RDX = 0x2, RBX = 0x3,
43    RSP = 0x4, RBP = 0x5, RSI = 0x6, RDI = 0x7,
44    R8  = 0x8, R9  = 0x9, R10 = 0xA, R11 = 0xB,
45    R12 = 0xC, R13 = 0xD, R14 = 0xE, R15 = 0xF,
46}
47reg_impls!(Rq);
48
49/// 16 or 32-byte SSE registers.
50#[allow(missing_docs)]
51#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
52pub enum Rx {
53    XMM0  = 0x0, XMM1  = 0x1, XMM2  = 0x2, XMM3  = 0x3,
54    XMM4  = 0x4, XMM5  = 0x5, XMM6  = 0x6, XMM7  = 0x7,
55    XMM8  = 0x8, XMM9  = 0x9, XMM10 = 0xA, XMM11 = 0xB,
56    XMM12 = 0xC, XMM13 = 0xD, XMM14 = 0xE, XMM15 = 0xF,
57}
58reg_impls!(Rx);
59
60/// 8-byte control registers.
61#[allow(missing_docs)]
62#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
63pub enum RC {
64    CR0  = 0x0, CR1  = 0x1, CR2  = 0x2, CR3  = 0x3,
65    CR4  = 0x4, CR5  = 0x5, CR6  = 0x6, CR7  = 0x7,
66    CR8  = 0x8, CR9  = 0x9, CR10 = 0xA, CR11 = 0xB,
67    CR12 = 0xC, CR13 = 0xD, CR14 = 0xE, CR15 = 0xF,
68}
69reg_impls!(RC);
70
71// The other register families are the same as 32-bit X86. (Although access size for Debug regs is 8-byte)
72pub use crate::x86::{Rh, Rf, Rm, Rs, RD, RB};
73
74#[cfg(test)]
75mod tests {
76    use super::Rq::*;
77    use crate::Register;
78
79    #[test]
80    fn reg_code() {
81        assert_eq!(RAX.code(), 0);
82    }
83
84    #[test]
85    fn reg_code_from() {
86        assert_eq!(u8::from(R11), 11);
87    }
88}
dynasmrt/x64.rs

dynasmrt/
x64.rs
