dynasmrt

Module riscv

Source
Expand description

Runtime support for the 32-bit and 64-bit RISC-V architecture assembling targets.

The riscv instruction sets feature 16-bit and 32-bit width instructions. It features relocations up to 20 bits in size in a single instruction, or 32 bits in size using sequences of two instructions.

The core relocation behaviour for these architecture is provided by the RiscvRelocation type.

Next to that, this module contains the following:

§Type aliases

Several specialized type aliases of the generic Assembler are provided as these are by far the most common usecase.

§Enums

There are enumerations of every RISC-V register family. These enums implement the Register trait and their discriminant values match their numeric encoding in dynamic register literals.

Note: The presence of some registers listed here is purely what is encodable. Check the relevant architecture documentation to find what is architecturally valid.

§Functions

This module contains handlers for error conditions in the case where a dynamically selected register is invalid, or a dynamically encoded immediate is out of range. These panic with a friendly error message if any of these conditions happen at runtime.

Enums§

  • 4, 8 or 16-byte floating point registers
  • 4 or 8-byte general purpopse registers, where X0 is the zero register When using the RV32/64E profile, only the first 16 registers are valid
  • Relocation implementation for the RV32 and RV64 architectures.

Functions§

Type Aliases§

  • A RISC-V Assembler. This is aliased here for backwards compatability.
  • A RISC-V AssemblyModifier. This is aliased here for backwards compatability.
  • A RISC-V UncommittedModifier. This is aliased here for backwards compatability.